Assertion: `X_C < X_L, phi` is positive and the circuit is predominantly capacitive. The current in the circuit leads the source voltage.
Reason: If `X_C < X_L, phi` is negative and the circuit is predominantly inductive. The current in the circuit lags the source voltage.
Options:
(a) Both A and R are true and R is the correct explanation of A.
(b) Both A and R are true but R is not the correct explanation of A.
(c) A is true but R is false.
(d) A is false and R is also false.